Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET

ABSTRACT

In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 μm. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and incorporates herein by referenceJapanese Patent Application No. 2001-341906 filed on Nov. 7, 2001.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device including aCMOSFET and a bipolar transistor and to a method for manufacturing thesemiconductor device. In the method, the bipolar transistor is formed bytaking advantage of steps for forming a well region, source regions, anddrain regions of the CMOSFET.

With a manufacturing process for a semiconductor device called a Bi-CMOSIC, in which bipolar transistors and CMOSFETs are formed on the samesubstrate, there is a technology for forming, for example, base regionsof the bipolar transistors using diffusion regions for forming wells forthe CMOSFETs and for forming emitter regions using diffusion regions forforming the source and drain regions in order to reduce the number ofprocess steps. In a semiconductor device 1 shown in FIG. 24, asilicon-on-insulator (SOI) substrate is included., and a CMOSFET 4 and abipolar transistor 5 are located over an insulating film 3 on a siliconsubstrate 2.

An SOI layer included in the SOI substrate includes a high impurityconcentration n-type silicon layer 6 and a low impurity concentrationn-type silicon layer 7 on the insulating film 3, and the transistors 4,5 of the device 1 are isolated by trenches 8 and by LOCOS 9 in a surfaceof the device 1. The CMOSFET 4 includes p channel-type and nchannel-type MOSFETs 4 a, 4 b, in which an n-type well 10 and a p-typewell 11 are included, respectively. Source and drain regions 12, 13 areincluded in the n-type well 10 and the p-type well 11, respectively.Each gate electrode 15 is located on a gate oxide film 14. Contact holesare located in an insulating film 16. Aluminum electrodes 17 are inelectric-contact with the source and drain-regions 12, 13.

An npn transistor 5 includes a low impurity concentration n-type siliconlayer 7 as a collector region, in a surface of which a p-type baseregion 18 is located. An n-type emitter region 19 and a base contactregion 20 are located in a surface of the p-type base region 18. Acollector contact region 21 is also located in the surface of thesilicon layer 7.

The semiconductor device 1 is formed by the following process flow,which is shown in FIGS. 25A to 25G. As shown in FIG. 25A, an SOIsubstrate 210, in which n-type single crystal silicon layers 6, 7 arelocated on an insulating layer 3, is prepared. Then, trenches 8 areformed outside the areas where for transistors 4, 5 are formed, as shownin FIG. 25B. Then, wells 10, 11 are formed using a known CMOSFETprocess. Simultaneously, base region 18 is formed, as shown in FIG. 25C.Next, as shown in FIG. 25D, LOCOS 9 are formed, and a gate oxide film 14and gate electrodes 15 are formed, as shown in FIG. 25F.

Using the gate electrodes 15 as a mask, the source and drain regions 12,13 of MOSFETs 4 a, 4 b are formed, as shown FIG. 25F. Simultaneously, anemitter region 19, a base contact region 20, and a collector contactregion 21 are formed. Finally, an insulating film 16 and the aluminumelectrodes 17 are formed to complete a Bi-CMOSFET semiconductor device1.

Because the npn transistor 5 is formed using a CMOSFET manufacturingprocess, the Bi-CMOSFET semiconductor device 1 has the followingdrawback with the characteristics of the npn transistor 5. The baseregion 18 of the transistor 5 is simultaneously formed at the step forforming the p-type well 11, so the surface impurity concentration of thebase region 18 is generally relatively low. Therefore, thecharacteristics of the transistor 5 can shift due to a slight shift inthe amount of charges at the interface between the p-type base region 18and the insulating film 16, which is made of SiO₂, under a certainbiasing condition for driving the transistor 5. The interface is shownwith small x-marks in FIG. 24. As a result, the characteristics of thetransistor 5 become unstable, and operating errors are caused in somecircuit designs.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above aspects. Afirst object of the present invention is to provide a semiconductordevice that is relatively stable in the device characteristics, whichare affected by the impurity concentration at a surface of a baseregion, even when a bipolar transistor and a CMOSFET is simultaneouslyformed in a device using a CMOSFET process. A second object is toprovide a method of manufacturing the semiconductor device.

In the present invention, a CMOSFET and a bipolar transistor are formedinto a single unit on a substrate. The steps for forming a well region,source regions, and drain regions of the CMOSFETs are also used forforming the bipolar transistors, and one of the steps is used forintroducing impurities of the same conductivity type in a surface of abase region of the bipolar transistor in order to form a high impurityconcentration area in the surface.

Alternatively, the surface of the base region is exposed by ultravioletrays in order to reduce the amount of charges at the interface betweenthe base region and an insulating film located on the surface of thebase region.

Alternatively, after an insulating film is formed at the surface of thebase region of the bipolar transistor, a hydrogen barrier film is formedsuch that the hydrogen barrier film covers the surface of the baseregion.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription made with reference to the accompanying drawings. In thedrawings:

FIG. 1 is a partial cross-sectional view of a semiconductor deviceaccording to a first embodiment of the present invention;

FIG. 2 is a graph showing the simulation results obtained for the Gummelcharacteristics of an npn transistor having a surface impurityconcentration of 2×10¹⁶ cm⁻³ in a base region of the transistor in bothcases with and without positive fixed charges at an interface between abase region and an insulating film located on the base region;

FIG. 3 is a graph showing the simulation results for the direct currentamplification (h_(FE)) characteristics of an npn transistor with respectto impurity concentration at the surface of a base region of thetransistor in both cases with and without the positive fixed charges;

FIG. 4 is a graph showing the simulation results for the direct currentamplification (h_(FE)) characteristics of an npn transistor with respectto the distance d between a high impurity concentration region and anemitter region of the transistor in both cases with and without charges;

FIG. 5 is a graph showing the actually measured results for the directcurrent amplification (h_(FE)) characteristics of an npn transistor thathas the same structure as used for the simulation of FIG. 4;

FIG. 6 is a graph showing the correlation between the reverse biasbreakdown voltage and distance between a high impurity concentrationregion and an emitter region of an npn transistor;

FIG. 7 is a graph showing the correlation between the changes in outputvoltage and time with various distances between a high impurityconcentration region and an emitter region of an npn transistor;

FIG. 8A is a partial cross-sectional view of a first variation of asemiconductor device according to a second embodiment, FIG. 8B is a planview of a bipolar transistor in the first variation, FIG. 8C is apartial cross-sectional view of a second variation of the semiconductordevice according to the second embodiment, FIG. 8D is a plan view of abipolar transistor in the second variation;

FIGS. 9A to 9P are cross-sectional views showing the structure of asemiconductor device according to a third embodiment in themanufacturing process of the device;

FIG. 10 is a cross-sectional view of a bipolar transistor of asemiconductor device according to a fourth embodiment;

FIG. 11 is a partial cross-sectional view of a semiconductor deviceaccording to a fifth embodiment;

FIG. 12 is a partial cross-sectional view of a semiconductor deviceaccording to a sixth embodiment;

FIG. 13 is a graph showing the correlation between the direct currentamplification factor and the collector current without any ultravioletradiation;

FIG. 14 is a graph showing the correlation between the direct currentamplification factor and the collector current with ultravioletradiation;

FIG. 15 is a partial cross-sectional view of a semiconductor deviceaccording to a seventh embodiment;

FIG. 16A is a partial cross-sectional view of a semiconductor deviceaccording to an eighth embodiment and FIG. 16B is a plan view of abipolar transistor in the device according to the seventh embodiment;

FIG. 17 is a cross-sectional view of a bipolar transistor in asemiconductor device according to a ninth embodiment;

FIG. 18A is a cross-sectional view of a bipolar transistor in asemiconductor device according to a tenth embodiment and FIG. 18B is aplan view of the bipolar transistor according to the tenth embodiment;

FIG. 19A is a cross-sectional view of a bipolar transistor in asemiconductor device according to an eleventh embodiment and FIG. 19B isa plan view of the bipolar transistor according to the eleventhembodiment;

FIG. 20 is a cross-sectional view of a bipolar transistor in asemiconductor device according to a twelfth embodiment;

FIG. 21 is a circuit diagram according to a thirteenth embodiment;

FIG. 22 is another circuit diagram according to the thirteenthembodiment;

FIG. 23 is another circuit diagram according to the thirteenthembodiment;

FIG. 24 is a cross-sectional view of a proposed semiconductor device;and

FIGS. 25A to 25G are cross-sectional views showing the structure of thedevice in FIG. 24 in the manufacturing process of the device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in detail with reference tovarious embodiments.

First Embodiment

As shown in FIG. 1, a Bi-CMOS semiconductor device 31 includes a CMOSFET34 and a bipolar transistor 35. The CMOSFET 34 and the transistor 35 arelocated on an insulating film 33, which is located on a siliconsubstrate 32.

The Bi-CMOS semiconductor device 31 is formed from an SOI substrate,which has an SOI layer including a high impurity concentration n-typesilicon layer 36 and a low impurity concentration n-type silicon layer37, impurity concentration of which is, for example, approximately1×10¹⁵ cm⁻³. The CMOSFET 34 and the transistor 35 include the siliconlayers 36 and 37. The CMOSFET 34 and the bipolar transistor 35 aresurrounded and isolated by the trenches 38, respectively. Furthermore,the CMOSFET 34 and the bipolar transistor 35 are isolated bylocal-oxidation-of-silicon (LOCOS) areas 39 at the surface of the device31. The CMOSFET 34 includes an n channel MOSFET 34 a and a p channelMOSFET 34 b. A p-type well 40, which has an impurity concentration of,for example, approximately 4×10¹⁶ cm⁻³, and an n-type well 41 arelocated in the low impurity concentration n-type layer 37. N-type sourceand drain regions 42 are located in the p-type well 40. P-type sourceand drain regions 43 are located in the n-type well 41.

Gate electrodes 45 are made of polycrystalline silicon. Each gateelectrode 45 is located on a gate insulating film 44, which is locatedabove each channel between the source region and the drain region 42,43. The surface of the CMOSFET 34 is covered by an insulating film 46,and aluminum electrodes 47 are in electric contact with the source anddrain regions 42, 43 through contact holes in the insulating film 46.

In the bipolar transistor 35, a p-type base region 48, which has animpurity concentration of, for example, approximately 4×10¹⁶ cm⁻³, islocated in a surface of the low impurity concentration n-type layer 37.A high impurity concentration n-type emitter region 49, which has animpurity concentration of, for example, approximately 1×10²⁰ cm⁻³, islocated in a surface of the p-type base region 48. In addition, a highimpurity concentration p-type base region 50, which has an impurityconcentration of, for example, approximately 1×10²⁰ cm⁻³, is located inthe surface of the p-type base region 48. The high impurityconcentration p-type base region 50 is extends from an end of the LOCOS39 to a position having a distance d from an end of the emitter region49. A high impurity concentration n-type collector contact region 51 islocated in a surface of the low impurity concentration n-type layer 37.The surface of the bipolar transistor 35 is also covered by aninsulating film 46, and aluminum electrodes 47 are in electric contactwith the emitter region 49, the base region 50, and the collectorcontact region 51 through contact holes in the insulating film 46.

In the Bi-CMOS semiconductor device 31, the base region 48 of thebipolar transistor 35 is simultaneously formed when the p-type well 41of the CMOSFET 34 is formed. Furthermore, the emitter region 49 and thecollector contact region 51 are simultaneously formed when the n-typesource and drain regions 42 are formed. The high impurity concentrationp-type base region 50 is simultaneously formed when the p-type sourceand drain regions 43 are formed.

In the Bi-CMOS semiconductor device 31, the impurity concentration ofthe p-type well 40 is lower than the concentration required for the baseof a bipolar transistor. The impurity concentration is, for example,approximately 4×10¹⁶ cm⁻³. Therefore, it is essentially undesired thatthe base region 48 is formed at the step of forming the p-type well 40in terms of device characteristics. However, the surface area of thebase region 48 is mostly covered by the emitter region 49 and the highimpurity concentration p-type base region 50, and the base region 48 isin contact with the insulating film 46 at the space of as short as 1 to2 μm between the emitter region 49 and the base region 50. Therefore,the instability in operating characteristics of the bipolar transistor35, which is caused by a relatively low impurity concentration at thesurface of the base region 48, is improved, and the operatingcharacteristics becomes relatively stable. The reason is as follows.

In the Bi-CMOSFET semiconductor device 1 of FIG. 24, the impurityconcentration at the surface of the base region 18 can be as low as1×10¹⁸ cm⁻³ or less for the sake of the design of the CMOSFET 4 whensimultaneously forming the base region 18 of the bipolar transistor 5and the p-type well region 11 of the CMOSFET 4. In that case, theoperating characteristics stray from desired values, because an n-typeinversion layer can be formed at the surface of the base region 18 whenthe bipolar transistor 5 is driven under certain biasing conditions, orwhen an amount of the positive fixed charges increases at the Si—SiO₂interface, which is located between the base contact region 20 and theemitter region 19, in the manufacturing process of the device 1.

The inventor of the present invention conducted the followingsimulations to study the above problem. As shown in FIG. 2, thecollector currents increase due to the positive fixed charges. Thedirect current gain h_(FE) is expressed in the equation, h_(FE)=Ic/Ib,where Ib is a base current, and Ic is a collector current. In general,the base current Ib increases when the number of recombination sitesincreases due to a higher density of defects such as a crystal defectand a dangling bond in the emitter-base depletion layer and thecorresponding recombination current increases. On the other hand, thecollector current Ic changes with a change in the transistor structuresuch as impurity concentrations, depths, and sizes of the base regionand the emitter region. The simulation results show that the basecurrent Ib substantially does not change under the effect of thepositive fixed charges while the collector current Ic increases. Inother words, The Gummel characteristics in FIG. 2 show that thetransistor structure changes under the effect of the positive fixedcharges when the impurity concentration is too low at the surface of thebase region.

Furthermore, as shown in FIG. 3, the above problems encountered with theproposed device of FIG. 24 can be addressed by raising the impurityconcentration at the surface of the base region. The first embodiment isbased on the above simulation results, so the bipolar transistor 35includes the high impurity concentration p-type base region 50 forraising the impurity concentration at the surface of the base region 48.

In the Bi-CMOS semiconductor device 31 of FIG. 1, the distance d betweenthe emitter region 49 and the high impurity concentration p-type baseregion 50 is 1 to 2 μm. Therefore, the impurity concentration isrelatively high across the substantially entire surface of the baseregion 48. The position for forming the high impurity concentrationp-type base region 50 will be described in detail. As shown in FIG. 4,h_(FE) is relatively stable, with or without the charges, when thedistance d is 1 to 2 μm. As shown in FIG. 5, the h_(FE) values go downrapidly when the distance d is shorter than 1 μm. Furthermore, as shownin FIG. 6, the reverse bias breakdown voltage Vz (V) between the emitterregion and the base region changes with the distance d, and thebreakdown voltage goes down rapidly when the distance d is shorter than1 μm. Therefore, the lower limit for the distance d should be 1 μm. Asshown in FIG. 7, substantially no changes in the output voltage areobserved and the output voltage becomes stable when the distance d isshorter than 2 μm. From the results shown in FIGS. 4 to 7, it isconcluded that an optimal range for the distance d should be 1 to 2 μm.

In the Bi-CMOS semiconductor device 31 of FIG. 1, shifts in thecharacteristics of the bipolar transistor 35, which is caused byotherwise a low impurity concentration at the surface of the base region48, is improved by forming the high impurity concentration p-type baseregion 50 at the surface of the base region 48. Moreover, the productioncost is lowered because the high impurity concentration p-type baseregion 50 is simultaneously formed when the p-type source and drainregions 43 are formed in the n-type well region 41 of the CMOSFET 34.Furthermore, the distance d between the high impurity concentrationp-type base region 50 and the emitter region 49 is set at 1 to 2 μm, sothe shifts in the device characteristics are improved while sustainingthe direct current amplification h_(FE) and the breakdown voltage Vz.

Second Embodiment

Bi-CMOS semiconductor devices 52 of FIGS. 8A to 8D are different instructure of the high impurity concentration p-type base region from theBi-CMOS semiconductor device 31 of FIG. 1. In the Bi-CMOS semiconductordevice 52 of FIGS. 8A and 8B, a high impurity concentration p-type baseregion 54 is formed to surround an emitter region 49 in a bipolartransistor 53 of the Bi-CMOS device 52, as shown in FIG. 8B, in whichaluminum electrodes 47 are not illustrated. In the Bi-CMOS semiconductordevice 52 of FIGS. 8 c and 8 d, a bipolar transistor 53 includes a highimpurity concentration p-type base contact region 54 a, on which analuminum electrode 47 is formed, and a high impurity concentrationp-type base region 54 b that surrounds an emitter region 49, as shown inFIG. 8D, in which aluminum electrodes 47 are not illustrated.

In the Bi-CMOS semiconductor devices 52 of FIGS. 8A to 8D, the size ofthe surface, at which the base region 48 is in contact with theinsulating film 46 is smaller than in the Bi-CMOS semiconductor device31 of FIG. 1, so the changes in device characteristics, which is causedby an inversion at the surface, is further reduced and stabilized in theBi-CMOS semiconductor devices 52 of FIGS. 8A to 8D.

Third Embodiment

As shown in FIG. 9P, a Bi-CMOS semiconductor device 55 differs from theBi-CMOS semiconductor devices 52 of FIGS. 8A to 8D in that a selfalignment mask pattern 56 is included in order to precisely control thedistance d between a high impurity concentration p-type base region 54and an emitter region 49. An additional process step is not required forforming the self alignment mask pattern 56.

As shown in FIG. 9P, the self alignment mask pattern 56, which is madeof a polycrystalline silicon film, is located over the surface of a baseregion 48 between the high impurity concentration p-type base region 54and the emitter region 49 in addition to the structures of the Bi-CMOSsemiconductor devices 52 of FIGS. 8A to 8D. In FIG. 9P, a passivationfilm 57 for protecting the device surface including aluminum electrodes47 is illustrated.

The manufacturing steps for forming the Bi-CMOS semiconductor device 55will be described. Firstly, an SOI substrate 58 shown in FIG. 9A isprepared. A silicon substrate 32 is several hundred microns inthickness. A high impurity concentration n-type silicon layer 36 and alow impurity concentration n-type silicon layer 37 are located on aninsulating film 33 made of a silicon oxide film, which is located on thesubstrate 32. Then, trenches 38 for device isolation are formed in theSOI substrate 58, as shown in FIG. 9B. The trenches 38 are formed byforming grooves, depositing an insulating film on the sidewalls definingthe grooves, and filling the grooves with polycrystalline silicon forplanarization.

Next, an ion implanted area 59, corresponding to an n-type well region41, is formed by ion implanting an n-type impuritiy, as shown in FIG.9C. Similarly, an ion implanted area 60, corresponding to a p-type wellregion 40, is formed by ion implanting a p-type impurity, as shown inFIG. 9D. At the step for forming the p-type well region 40, an ionimplanted area 61, corresponding to a p-type base region 48 of a bipolartransistor 53, is also formed.

Next, the p-type well region 40, the n-type well region 41, and thep-type base region 48 are formed from the ion implanted areas 59 through61 by driving in the impurities at a diffusion step, as shown in FIG.9E. LOCOS 39 are formed at predetermined locations on the substratesurface for device isolation at the surface, as shown in FIG. 9F. Next,a gate oxide film 44 is formed on the surface of the substrate of FIG.9F, and gate electrodes 45 are formed from a polycrystalline siliconfilm, as shown in FIG. 9G.

At the same time, a self alignment mask pattern 56 is also formed fromthe polycrystalline silicon film on the surface of the bipolartransistor 53. The mask pattern 56 has a width corresponding to thedistance d between an emitter region 49 and a high impurityconcentration p-type base region 50 of the bipolar transistor 53.

Next, a photo resist 62 is patterned to form p-type source and drainregions 43 in the n-type well region 41 and a high impurityconcentration p-type base region 54 in the p-type base region 48, asshown in FIG. 9H. The photo resist 62 is formed to be slightly offsetfrom the edges of the mask pattern 56. As a result, the positions of theedges of the high impurity concentration p-type base region 54 can bealigned with a higher precision than an alignment precision achieved bythe photo resist 62. Next, p-type impurities are introduced by ionimplanting into the openings in the photo resist 62 to form the p-typesource and drain regions 43 and the high impurity concentration p-typebase region 54, as shown in FIG. 9I. Then, the photo resist 62 isstripped off, as shown in FIG. 9J, and a photo resist 63 is patternedfor forming n-type source and drain regions 42, the high impurityconcentration n-type emitter region 49, and a collector contact region51, as shown in FIG. 9K. The edges of the photo resist 63 are slightlyoffset from the edges of the mask pattern 56. Then, n-type impuritiesare introduced by ion implanting to form the n-type source and drainregions 42, the high impurity concentration n-type emitter region 49,and the collector contact region 51, as shown in FIG. 9L.

Then, the photo resist 63 is stripped off, as shown in FIG. 9M, and aninsulating film 46 is formed with a BPSG film, as shown in FIG. 9N.Contact holes are opened by photolithography and etching, and aluminumelectrodes 47 are formed, as shown in FIG. 90. Finally, a passivationfilm 57 is formed, and openings are made at the electrode pads tocomplete the wafer process, as shown in FIG. 9P.

The distance d between the emitter region 49 and the high impurityconcentration p-type base region 54 can be controlled precisely by usingthe self alignment mask pattern 56 to achieve a high degree of processcontrol. Furthermore, the production cost is lowered by simultaneouslyforming the gate electrodes 45 of the CMOSFET 34 and the self alignmentmask pattern 56 from the same polycrystalline silicon film because noadditional process steps are required.

Fourth Embodiment

As shown in FIG. 10, a bipolar transistor 65 in a Bi-CMOS device 64 hasan emitter support area 66 as a self alignment mask pattern. Althoughnot shown, the Bi-CMOS device 64 includes a CMOS 34 having the samestructure as the CMOS 34 in FIG. 1.

In the bipolar transistor 65, an emitter region 49 is formed beforep-type source and drain regions 43 of the CMOS 34 are formed, and theemitter support area 66, which is electrically connected to the emitterregion 49, is formed after a gate insulating film 44 is formed. Theemitter support area 66 is formed using a polycrystalline silicon filmat the same time as gate electrodes 45 of the CMOS 34 are formed, and anelectric contact is established with the emitter support area 66 througha contact hole opened in the gate insulating film 44 in an areacorresponding to the emitter region 49. One end of the emitter supportarea 66 extends out of the emitter region 49 by a predetermined distanced1.

Next, when forming the high impurity concentration p-type base region 50by introducing impurities, the emitter support area 66 is used as a selfalignment mask pattern. The distance d between the high impurityconcentration p-type base region 50 and the emitter region 49 isslightly smaller than d1. Therefore, a desired distance d is achievedwith a high precision by taking into account how much smaller thedistance d will be than the predetermined distance d1 of the emittersupport area 66 and compensating the extension d1 in advance.

Fifth Embodiment

As shown in FIG. 11, a Bi-CMOS semiconductor device 67 differs from theBi-CMOS semiconductor device 31 of FIG. 1 in that a double diffusedCMOSFET (DCMOSFET) 69 is included in addition to a bipolar transistor 68and a CMOS 34 as a single unit in the Bi-CMOS 67. A step for forming theDCMOSFET 69 is used for forming a high impurity concentration p-typebase region 70 of the bipolar transistor 68.

In the manufacturing process of the Bi-CMOS 67, a drain region 71 of theDCMOSFET 69 and an n-type well region 41 of the CMOSFET 34 aresimultaneously formed. Then, when a p-type region 72, which makes up achannel and has a higher level of impurity concentration than the p-typewell 40, is formed, the high impurity concentration p-type base region70 is simultaneously formed in a base region 48 of the bipolartransistor 68. Next, a gate oxide film 44 and a gate electrode 73 of theDCMOSFET 69 are formed, and a p-type channel contact region 74, ann-type source region 75, and a drain contact region 76 are formed in theDCMOSFET 69. Subsequently, an insulating film 46 and aluminum electrodes47 are formed. One of the aluminum electrodes 47 that is formed to spanover the p-type channel contact region 74 and the n-type source region75 is a source electrode. Another one of the aluminum electrodes 47 thatis formed on the drain contact region 76 is a drain electrode. The gateelectrode 73 is electrically connected to the outside through a gateelectrode metal, which is not illustrated.

In the manufacturing process of the Bi-CMOS 67, the high impurityconcentration p-type base region 70 is formed in the bipolar transistor68 without adding extra steps. The interface between the high impurityconcentration p-type base region 70 and the insulating film 46 are sostable that relatively good device characteristics of the bipolartransistor 68 are acquired in the Bi-CMOS 67.

Sixth Embodiment

As shown in FIG. 12, in the method according to the sixth embodiment,ultraviolet rays are exposed to a Bi-CMOSFET semiconductor device havingthe same structure as the Bi-CMOSFET semiconductor device 31 of FIG. 1to remove hydrogen atoms from the interface, which is a Si—SiO₂interface, between a high impurity concentration p-type base region 50and an insulating film 46 and from the interface between a p-type baseregion 48 and the insulating film 46.

Positive fixed charges, which is denoted by “X” marks in FIG. 12, aregenerated at the interface. Changes in the amount of the positive fixedcharges can be attributed to shifts of hydrogen atoms, which are bondedto silicon with dangling bonds at the interface, under certain biasingconditions used for driving the bipolar transistor 35, or due to themanufacturing process of the Bi-CMOSFET semiconductor device.

It is known that when an insulating film containing a large amount ofhydrogen atoms such as a silicon nitride film formed by a plasma CVDmethod is used as a passivation film 57, hydrogen atoms diffuse to theinterface during a thermal treatment step. Therefore, devicecharacteristics of the bipolar transistor 35 are further stabilized byproviding the Bi-CMOSFET semiconductor device 1 of FIG. 24 with atreatment step for reversing the adverse effects of such hydrogen atoms.

As shown in FIG. 12, after the passivation film 57 is formed andannealed, the passivation film 57 is exposed to ultraviolet rays toremove the hydrogen atoms located at the interface by adding energy tothe hydrogen atoms. The passivation film 57 needs to transmitultraviolet rays to expose the Si—SiO₂ interface to the ultraviolet raysand provide enough energy with the hydrogen atoms.

By removing the hydrogen atoms from the Si—SiO₂ interface withultraviolet rays after the formation and annealing of the passivationfilm 57, the bipolar transistor 35 becomes more stable in the devicecharacteristics. Ten samples that had not been exposed to ultravioletrays showed changes in device characteristics between the initialconditions and after 300 hours of operation, as shown in FIG. 13. On theother hand, three samples that had been exposed to ultraviolet raysshowed substantially no changes in the device characteristics betweenthe initial conditions and after 300 hours of operation, as shown inFIG. 14.

Although ultraviolet rays are exposed to the Bi-CMOSFET semiconductordevice having the same structure as the Bi-CMOSFET semiconductor device31 of FIG. 1 in the method of FIG. 12, the benefit of the UV irradiationcan be applied to the Bi-CMOSFET semiconductor device 1 of FIG. 24,which has a wider spacing between the high impurity concentration p-typebase region 20 and the emitter region 19.

Seventh Embodiment

As shown in FIG. 15, a Bi-CMOSFET semiconductor device 77 differs fromthe Bi-CMOSFET semiconductor device of FIG. 12 in that an EPROM 78 isincluded in the Bi-CMOS device 77. The EPROM 78 has a structure forerasing contents of the memory under an ultraviolet radiation, and, forthis reason, a film that is highly transparent to ultraviolet rays isused as a passivation film 57, just as in the Bi-CMOSFET semiconductordevice of FIG. 12.

The EPROM 78 has a standard EPROM structure. In the EPROM 78, an n-typewell region 79, which is similar to an n-type well region 41, is locatedin a low impurity concentration n-type silicon layer 37, and p-typesource and drain regions 80 are located in the n-type well region 79. Afloating gate 81 is located above a gate insulating film 44, and acommon gate 82 is located on the floating gate 81 with anotherinsulating film in-between.

Each time the Bi-CMOS 77 is exposed to ultraviolet rays for erasing thememory content in the EPROM 78, hydrogen atoms at the interface betweena base region 48 and an insulating film 46 in a bipolar transistor 35are removed. Therefore, the bipolar transistor 35 of the Bi-CMOS 77 hasmore stable device characteristics than the bipolar transistor 35 of theBi-CMOSFET semiconductor device 31 in FIG. 1.

Eighth Embodiment

As shown in FIGS. 16A and 16B, a Bi-CMOSFET semiconductor device 83differs from the Bi-CMOSFET semiconductor device 31 in FIG. 1, whichincludes the high impurity concentration p-type base region 50 having adistance of 1 to 2 μm from the emitter region 49, in that apolycrystalline silicon film 85 is located in the bipolar transistor 84as a hydrogen barrier layer.

In the method of FIG. 12, ultraviolet rays were exposed to theBi-CMOSFET semiconductor device of FIG. 12 for removing the hydrogenatoms, which are bonded to silicon with dangling bonds and undesirablyaffect the characteristics of the bipolar transistor 35, from theSi—SiO₂ interface. On the other hand, in the Bi-CMOSFET semiconductordevice 83, the polycrystalline silicon film 85 is included in order toprevent the hydrogen atoms existing in a passivation film 57, which isnot shown in FIGS. 16A and 16B, from traveling to the interface betweena base region 48 and an insulating film 44 of FIG. 16A and from changingthe characteristics of a bipolar transistor 84.

The bipolar transistor 84 includes an emitter region 49 and a basecontact region 50 a in the base region 48. However, the polycrystallinesilicon film 85, which is the hydrogen barrier film, is located abovethe interface between the base region 48 and the insulating film 44 ofFIG. 16A in such a way that the polycrystalline silicon film 85surrounds the emitter region 49 as viewed in FIG. 16B. Thepolycrystalline silicon film 85 is simultaneously formed at the step offorming gate electrodes 45 of a CMOSFET 34 of FIG. 16A. Therefore, theBi-CMOSFET semiconductor device 83 of FIG. 16A can be manufactured usingthe manufacturing process shown by FIGS. 25A to 25G, which are the onesfor the proposed semiconductor device 1 of FIG. 24, without anyadditional steps.

Ninth Embodiment

As shown in FIG. 17, a Bi-CMOSFET semiconductor device 96 differs fromthe Bi-CMOSFET semiconductor device 83 of FIG. 16A in that a bipolartransistor 86 includes an emitter electrode 87, which is made of apolycrystalline silicon film, to function as a hydrogen barrier film.Although not shown, the Bi-CMOS device 96 includes a CMOSFET 34 havingthe same structure as the CMOSFET 34 in FIG. 16A. In the bipolartransistor 84 of FIG. 16 a, the polycrystalline silicon film 85 isfloating. In the bipolar transistor 86 of FIG. 17, on the other hand,the emitter electrode 87, which is in electric contact with the emitterregion 49, has the same function as the polycrystalline silicon film 85.

The emitter electrode 87 is simultaneously formed in the process forforming the CMOSFET 34, which is not shown. An emitter contact hole isformed in a gate insulating film 44. Then, the emitter electrode 87 isformed from a polycrystalline silicon film, which is also used forforming gate electrodes 45. The emitter electrode 87 is patterned insuch a way that an edge of the emitter electrode 87 extends toward andnear the edge of a base contact area 50 a. As a result, the emitterelectrode 87 is located above the interface between the base region 48and the insulating film 44 of FIG. 16A such that the interface issubstantially completely covered by the emitter electrode 87.

Therefore, the hydrogen atoms, which can otherwise bond to silicon atthe interface with dangling bonds and undesirably affect thecharacteristics of the bipolar transistor 86, are not allowed to travelfrom an insulating film 46 or a passivation film 57, which is not shownin FIG. 17, so the bipolar transistor 86 has relatively stable devicecharacteristics.

Tenth Embodiment

As shown in FIGS. 18A and 18B, a Bi-CMOSFET semiconductor device 97differs from the Bi-CMOSFET semiconductor device 83 of FIG. 16A in thata bipolar transistor 88 includes an aluminum electrode 47 a as a baseelectrode and as a hydrogen barrier film. Although not shown, theBi-CMOS device 97 includes a CMOSFET 34 having the same structure as theCMOSFET 34 in FIG. 16A. As shown in FIGS. 18A and 18A, the aluminumelectrode 47 a extends above the interface between a base region 48 andan insulating film 46 of FIG. 18A such that the interface issubstantially completely covered by the aluminum electrode 47 a toprevent hydrogen atoms from traveling to the interface from apassivation film 57, which is located on the aluminum electrode 47 aalthough not shown in FIG. 18A. Therefore, the bipolar transistor 88 hasrelatively stable device characteristics.

Eleventh Embodiment

As shown in FIGS. 19A and 19B, a Bi-CMOSFET semiconductor device 98differs from the Bi-CMOSFET semiconductor device 97 of FIGS. 18A and 18Bin that a bipolar transistor 89 includes an aluminum electrode 47 b asan emitter electrode and as a hydrogen barrier film. Although not shown,the Bi-CMOS device 97 includes a CMOSFET 34 having the same structure asthe CMOSFET 34 in FIG. 16A. As shown in FIGS. 19A and 19B, the aluminumelectrode 47 b extends above the interface between a base region 48 andan insulating film 46 of FIG. 19A such that the interface issubstantially completely covered by the aluminum electrode 47 b toprevent hydrogen atoms from traveling to the interface from apassivation film 57, which is located on the aluminum electrode 47 balthough not shown in FIG. 18A. Therefore, the bipolar transistor 88 hasrelatively stable device characteristics in the same manner as theBi-CMOSFET semiconductor device 97 of FIG. 18A.

Twelfth Embodiment

As shown in FIG. 20, a Bi-CMOSFET semiconductor device 99 differs fromthe Bi-CMOSFET semiconductor device 83 of FIG. 16A in that a bipolartransistor 90 includes a silicon nitride film 91 as a hydrogen barrierfilm. Although not shown, the Bi-CMOS device 97 includes a CMOSFET 34having the same structure as the CMOSFET 34 in FIG. 16A. The siliconnitride film 91 is deposited to cover the substantially entire bipolartransistor 90 after a gate oxide film 44 is formed. Then, an insulatingfilm 46, aluminum electrodes 47, and a passivation film 57, which isformed on the aluminum electrode 47 although not shown in FIG. 20.Therefore, the bipolar transistor 20 has relatively stable devicecharacteristics.

Thirteenth Embodiment

As shown in FIGS. 21 to 23, each application circuit 92, 93, 95 includesa pair of npn transistors, which are bipolar transistors Tr1 a and Tr2a, Tr1 b and Tr2 b, Tr1 c and Tr2 c. In each circuit 92, 93, 95, thebipolar transistors in the Bi-CMOS devices according to the firstthrough twelfth embodiments are used as the pair of transistors Tr1 aand Tr2 a, Tr1 b and Tr2 b, Tr1 c and Tr2 c to ensure the performanceparity between the pair in each circuits 92, 93, 95 and to achieve highperformance.

In each circuit 92, 93, 95, the amount of shifts in transistorcharacteristics of the pair during operation differs from each otherbecause each bipolar transistor is exposed to different biasingconditions during operation. Therefore, the balance in performancebetween the pair tends to be lost. Thus, all of the circuits 92, 93, 95require that the bipolar transistors of the pair offer stablecharacteristics in spite of varying biasing conditions.

The first application circuit 92 of FIG. 24 is designed to provide anoutput current Iout in response to an input current Iin, and a currentmirror circuit in the input stage of the first application circuit 92includes the pair of bipolar transistors Tr1 a, Tr2 a, which havetransistor characteristics identical with each other. The voltage Vce1between the collector and the emitter of the transistor Tr1 a, thecollector and the base of which are shorted, is equivalent to theforward bias voltage Vf between the base and the emitter of a bipolartransistor Tr3. Furthermore, the voltage Vce2 between the collector andthe emitter of the transistor Tr2 a on the output side is equal to abalance between a supply voltage Vcc and the voltage Vf between the baseand the emitter of the transistor Tr3.

Therefore, the voltages Vce1 and Vce2 are generally not equal to eachother, and so are biasing conditions between the transistors Tr1 a, Tr2a. When driven under such conditions, the shifts in devicecharacteristics of the transistors Tr1 a, Tr2 a, which are used as apair, becomes different from each other during operation and theperformance parity between the transistors Tr1 a, Tr2 a to break down,if the bipolar transistor 5 in the proposed Bi-CMOSFET semiconductordevice 1 of FIG. 24 is used for the pair of transistors Tr1 a, Tr2 a. Onthe other hand, stable circuit operation can be maintained in thecircuit 92 of FIG. 21 by using the bipolar transistors in the Bi-CMOSdevices according to the first through twelfth embodiments for the pairof transistors Tr1 a, Tr2 a.

The second application circuit 93 of FIG. 25 is a band gap circuit,which is used for outputting a reference voltage of, for example, 1.3 V.In the application circuit 93, currents of two different magnitudes arerespectively provided for transistors Tr1 b, Tr2 b in a band gap circuit94 of the second application circuit 93. The voltage drop due to aresistance R3, which is connected to the emitter of the transistor Tr1 band has an electric resistance of R3 ohms, leads to the followingrelationship between voltage Vbe1 and voltage Vbe2, which arerespectively the voltage between the base and the emitter of thetransistor Tr1 b and the voltage between the base and the emitter of thetransistor Tr2 b:Vbe2−Vbe1=R3×i,

-   -   where i is a current that flows through the resistance R3.

Therefore, the transistors Tr1 b, Tr2 b, which are used in a pair, aredriven under different conditions. Thus, stable circuit operation can bemaintained in the circuit 93 of FIG. 22 by using the bipolar transistorsin the Bi-CMOS devices according to the first through twelfthembodiments for the pair of transistors Tr1 b, Tr2 b.

The third application circuit 95 of FIG. 26 is also a band gap circuit,which is used for outputting a reference voltage Vref using a band gapcircuit. In the application circuit 95, transistor Tr1 c, Tr2 c, whichare used in a pair to make up the band gap circuit, operate under thefollowing conditions, and a collector voltage and a base voltage of thetransistor Tr2 c are inputted into input terminals to an op amp Op1:Vbe1=Vce1=Vce2+R3×i2, andi1/i2=R2/R3.

Therefore, the transistors Trlc, Tr2 c are driven under differentconditions. Thus, stable circuit operation can be maintained in thecircuit 95 of FIG. 23 by using the bipolar transistors in the Bi-CMOSdevices according to the first through twelfth embodiments for the pairof transistors Tr1 c, Tr2 c.

Other Embodiments

The present invention is not limited to the Bi-CMOS devices of the firstthrough twelfth and can also apply to the following variations.

Each method used in the Bi-CMOS devices of the first through twelfth ofthe embodiments can be used alone or in combinations. That is to say,the first group of methods used in the first through fifth embodiments,in which the high impurity concentration p-type base region 50 is used,the second group of methods used in the sixth and the seventhembodiments, in which ultraviolet rays are exposed to the Bi-CMOSdevices, and the third group of methods used in the eighth through thetwelfth embodiments, in which the hydrogen barrier film is used, may becombined with each other in various arrangements.

Although the transistors are isolated from each other by the trenches 38and the insulating layer 33 in the Bi-CMOS devices of the first throughtwelfth embodiments, the transistors may be isolated by PN junctions.

The polycrystalline silicon film 85, which is the hydrogen barrier film,is formed to surround the emitter region 49 in the Bi-CMOS device ofFIG. 16A. However, if the emitter region 49 is formed to be in contactwith the adjacent LOCOS 39 at one side of the emitter region 49, thepolycrystalline silicon film may surround the emitter region 49 on theremaining three sides.

Although only one of the aluminum electrodes 47, which are the baseelectrode 47 a and the emitter electrode 47 b, extends out in theBi-CMOS devices of FIGS. 18A and 19A, both the base electrode 47 a andthe emitter electrode 47 b may extend out.

1. A method for manufacturing a semiconductor device, which includes aCMOSFET and a bipolar transistor, wherein the bipolar transistor isformed on a substrate using steps of forming a well region of theCMOSFET and pairs of regions of the CMOSFET, each pair of which includesa source region and a drain region, on the substrate, and wherein a highimpurity concentration region is formed by introducing a first impurityof the same conductivity type as a base region of the bipolar transistorin a surface of the base region.
 2. The method in claim 1, wherein thebase region is formed using the step of forming the well region, whereinan emitter region of the bipolar transistor is formed by introducing asecond impurity at the step of forming one of the pairs of regions,wherein the high impurity concentration region is formed using the stepof forming another one of the pairs of regions.
 3. The method in claim2, wherein a self alignment mask pattern of the bipolar transistor isformed using a step of forming a gate electrode of the CMOSFET such thatthe self alignment mask pattern is located above a surface of the baseregion between the emitter region and the high impurity concentrationregion, and wherein the first and second impurities are introduced usingthe self alignment mask pattern as a mask material.
 4. The method inclaim 1, wherein the base region is formed using the step of forming thewell region, wherein an emitter region of the bipolar transistor isformed by introducing a second impurity, wherein an insulating film isformed on a surface of the bipolar transistor, wherein an emittersupport area is formed using a step of forming a gate electrode of theCMOSFET such that the emitter support area is in electric contact withthe emitter region and extends out of the emitter region on theinsulating film by a predetermined distance, and wherein the firstimpurity is introduced using the emitter support area as a maskmaterial.
 5. The method in claim 1, wherein an emitter region of thebipolar transistor is formed by introducing a second impurity, andwherein the high impurity concentration region and the emitter regionare formed such that a distance between the high impurity concentrationregion and the emitter region is 2 μm or shorter.
 6. The method in claim5, wherein the high impurity concentration region is formed such thatthe distance is 1 μm or longer.
 7. The method in claim 1, wherein thesemiconductor device further includes a DCMOSFET, wherein the baseregion is formed using the step of forming the well region, wherein thehigh impurity concentration region is formed using a step of forming aregion for channel of the DCMOSFET, and wherein an emitter region of thebipolar transistor is formed by introducing a second impurity in asurface of the high impurity concentration region at the step of formingone of the pairs of regions.
 8. The method in claim 1, wherein the highimpurity concentration region is formed to surround an emitter region ofthe bipolar transistor.
 9. The method in claim 1, wherein the surface ofthe base region is exposed to ultraviolet rays to reduce the amount ofcharges existing at an interface between the base region and aninsulating film, which is located on the surface of the base region.10-12. (Cancelled)
 13. A method for manufacturing a semiconductordevice, which includes a CMOSFET and a bipolar transistor, wherein thebipolar transistor is formed on a substrate using steps of forming awell region of the CMOSFET and pairs of regions of the CMOSFET, eachpair of which includes a source region and a drain region, on thesubstrate, wherein a base region of the bipolar transistor is formedusing the step of forming the well region, wherein a high impurityconcentration region is formed by introducing a first impurity of thesame conductivity type as the base region in a surface of the baseregion using the step of forming one of the pairs of regions, wherein anemitter region of the bipolar transistor is formed by introducing asecond impurity at the step of forming another one of the pairs ofregions, and wherein the high impurity concentration region and theemitter region are formed such that a distance between the high impurityconcentration region and the emitter region is 2 μm or shorter.
 14. Amethod for manufacturing a semiconductor device, which includes aCMOSFET and a bipolar transistor, wherein the bipolar transistor isformed on a substrate using steps of forming a well region of theCMOSFET and pairs of regions of the CMOSFET, each pair of which includesa source region and a drain region, on the substrate, and wherein asurface of a base region of the bipolar transistor is exposed toultraviolet rays to reduce the amount of charges existing at aninterface between the base region and an insulating film, which islocated on the surface of the base region.
 15. The method in claim 14,wherein the semiconductor device further includes an EPROM, and whereina passivation film, which is transparent to ultraviolet rays, is formedon the CMOSFET, the bipolar transistor, and the EPROM before the step ofexposing. 16-17. (Cancelled).
 18. The method in claim 14, wherein an SOIsubstrate is used for the substrate.
 19. A method for manufacturing asemiconductor device, which includes a CMOSFET and a bipolar transistor,wherein the bipolar transistor is formed on a substrate using steps offorming a well region of the CMOSFET and pairs of regions of theCMOSFET, each pair of which includes a source region and a drain region,on the substrate, and wherein an insulating film is formed on a surfaceof a base region of the bipolar transistor, and wherein a hydrogenbarrier film is formed on the insulating film to cover the surface ofthe base region. 20-21. (Cancelled)
 22. The method in claim 19, whereinthe base region is formed using the step of forming the well region,wherein an emitter region of the bipolar transistor is formed byintroducing a second impurity, wherein an emitter support area is formedas the hydrogen barrier film using a step of forming a gate electrode ofthe CMOSFET such that the emitter support area is in electric contactwith the emitter region and extends out of the emitter region by apredetermined distance.
 23. The method in claim 19, wherein the hydrogenbarrier film is formed using a portion of metal electrode of the bipolartransistor.
 24. The method in claim 23, wherein the metal electrode is abase electrode.
 25. The method in claim 23, wherein the metal electrodeis an emitter electrode.
 26. The method in claim 19, wherein thehydrogen barrier film is formed from a silicon nitride film. 27.(Cancelled)
 28. A semiconductor device comprising a CMOSFET and abipolar transistor, wherein the CMOSFET and the bipolar transistor arelocated on the same substrate, wherein a high impurity concentrationregion, which includes a impurity of the same conductivity type as abase region of the bipolar transistor with higher concentration than thebase region, is located in a surface of the base region.
 29. Thesemiconductor device in claim 28, wherein the high impurityconcentration region has substantially the same impurity concentrationas a pair of regions that includes a source region and a drain region ofthe CMOSFET.
 30. The semiconductor device in claim 29 further comprisinga self alignment mask pattern that is used to adjust the distancebetween an emitter region of the bipolar transistor and the highimpurity concentration region to a predetermined distance in amanufacturing process of the semiconductor device.
 31. The semiconductordevice in claim 28, wherein the bipolar transistor includes aninsulating film, wherein the insulating film is located on a surface ofthe base region, wherein the emitter support area is in electric contactwith an emitter region of the bipolar transistor and extends on theinsulating film by a predetermined dimension, and wherein the emittersupport area is used as a mask material for forming the high impurityconcentration region in a manufacturing process of the semiconductordevice. 32-33. (Cancelled)
 34. The semiconductor device in claim 28,wherein the semiconductor device further comprises a DMOSFET, andwherein the high impurity concentration region has substantially thesame impurity concentration as a region for channel of the DCMOSFET. 35.The semiconductor device in claim 28, wherein the high impurityconcentration region is located to surround an emitter region of thebipolar transistor.
 36. The semiconductor device in claim 28, wherein ahydrogen barrier film is located on a surface of the base region with aninsulating film in-between.
 37. The method in claim 36, wherein thehydrogen barrier film includes one film selected from the group thatconsists of a polycrystalline silicon film, an aluminum film, and asilicon nitride film.
 38. The semiconductor device in claim 28, whereinthe substrate is an SOI substrate.
 39. A semiconductor device comprisinga CMOSFET and a bipolar transistor, wherein the CMOSFET and the bipolartransistor are located on the same substrate, wherein a hydrogen barrierfilm is located on a surface of the base region with an insulating filmin-between. 40-41. (Cancelled)
 42. The semiconductor in claim 39,wherein the bipolar transistor includes an emitter support area, whereinthe emitter support area is in electric contact with an emitter regionof the bipolar transistor and extends on the insulating film by apredetermined dimension to function as the hydrogen barrier film. 43.The semiconductor in claim 39, wherein the hydrogen barrier film is aportion of a metal electrode of the bipolar transistor.
 44. Thesemiconductor device in claim 43, wherein the metal electrode is a baseelectrode.
 45. The semiconductor device of claim 43, wherein the metalelectrode is an emitter electrode.
 46. The semiconductor device in claim39, wherein the hydrogen barrier film is a silicon nitride film. 47.(Cancelled)